1. Field of the Invention
The present invention relates to semiconductor memory devices and in particular to a synchronous semiconductor memory device which operates synchronously with an external clock signal. More specifically, the present invention relates to a semiconductor memory device with an internally provided, synchronized signal generating circuit, such as a delay locked loop (DLL) circuit, which receives an external clock signal and generates an internal clock signal synchronized with the external clock signal.
2. Description of the Background Art
With the recent enhancement in the operating speeds of microprocessors (MPUs), a synchronous DRAM (SDRAM) or the like which operates synchronously with a clock signal has been used to provide rapid access to e.g. dynamic random access memory (DRAM) used as a main memory device. For such a semiconductor memory device operating synchronously with an external clock signal, a PLL or DLL circuit or the like for generating an internal clock signal synchronized with the external clock signal is typically mounted internal to the semiconductor memory device.
FIG. 17 is a schematic block diagram showing a configuration of a conventional, internally provided, synchronized signal generating circuit 3000 disclosed in Japanese Patent Laying-Open No. 9-293374.
Referring to FIG. 17, synchronized signal generating circuit 3000 includes: a delay circuit 3110 receiving an external clock signal Ext.CLK, delaying the received external clock signal Ext.CLK for a predetermined period of time and outputting the delayed external clock signal Ext.CLK; a phase comparator 3120 receiving external clock signal Ext.CLK and an output of delay circuit 3110 and detecting the phase difference between them; a switching decoder 3130 outputting a constant current supply switch signal CS depending on the detected result from phase comparator 3120; a variable, constant current supply circuit 3140 receiving signal CS to supply the value of a constant current corresponding thereto; and a delay control circuit 3150 outputting a control signal which controls the amount of delay of delay circuit 3110 depending on the value of the constant current output from variable, constant current supply circuit 3140.
Delay circuit 3110 includes inverter circuits Inv. 1 to Inv.n cascaded in n stages. Each inverter circuit Inv. i (i=l, 2, . . . n) is coupled with a power supply potential Vcc via a p-channel MOS transistor P1i and also with a ground potential GND via an n-channel MOS transistor N1i. p- and n-channel MOS transistors P1i and N1i have their respective gate potential levels controlled by delay control circuit 3150.
More specifically, delay control circuit 3150 controls the value of the current supplied to inverter circuits Inv. 1 to Inv.n configuring delay circuit 3110. In other words, the delay time at each inverter circuit Inv.i (i=1, 2, . . . n) varies depending on the control signal from delay control circuit 3150.
Variable, constant current supply circuit 3140 includes m internally provided, constant current supply circuits CS11, CS21, . . . , CSm1, and m internally provided, constant current supply circuits CS12, CS22, . . . , CSm2. Constant current supply circuit CS11 has one end connected to power supply potential Vcc and the other end connected to an output node 3140a via a switch circuit SW11 which is opened and closed in response to constant current supply switch signal CS.
The other constant current supply circuits CS21, . . . CSm1 each have one end similarly connected to power supply potential Vcc and the other end connected to output node 3140a via switch circuits SW21, . . . SWm1, respectively.
Constant current supply circuits CS12, CS22, . . . , CSm2 each have one end connected to output node 3140a via the respectively associated switch circuits SW12, SW22, . . . , SWm2 controlled by constant current supply switch signal CS to be opened and closed, and the other end connected to power supply potential GND.
Thus, the value of the constant current supplied to output node 3140a is increased when switch circuits SW11, SW21, . . . , SWm1 conduct, and it is decreased when switch circuits SW12, SW22, . . . , SWm2 conduct.
Thus, depending on the value of constant current supply switch signal CS, switch circuits SW11, SW21, . . . , SWm1 and switch circuits SW12, SW22, . . . , SWm2 are each opened/closed to output to output node 3140a a corresponding value of constant current depending on which delay control circuit 3150 operates, as described later.
Variable, constant current supply circuit 3140 also includes a free-running current supply 144 which normally supplies a predetermined value of constant current to output node 3140a. More specifically, a predetermined free-running current is always supplied to the output node while switch circuits SW11 to SWm1 and SW12 to SWm2 are all in the non-conductive state.
Delay control circuit 3150 includes: an n-channel MOS transistor N31 having its drain connected to output node 3140a and its source connected to ground potential GND; and an n-channel MOS transistor N32 having its source connected to ground potential GND and its gate connected to the gate of n-channel MOS transistor N31. The drain and gate of n-channel MOS transistor N31 are connected to each other, and n-channel MOS transistors N31 and N32 configure a current mirror circuit.
Delay control circuit 3150 also includes a p-channel MOS transistor P31 having its source connected to power supply potential Vcc and its drain connected to the drain of n-channel MOS transistor N32. The gate of n-channel MOS transistor N32 is connected to the gates of n-channel MOS transistors N11 to N1n of delay circuit 3110, and the value of the drain current flowing through n-channel MOS transistors N11 to N1n is controlled depending on the value of the current flowing through n-channel MOS transistors N31 and N32 configuring a current mirror circuit.
The gate of p-channel MOS transistor P31 is connected to the gates of p-channel MOS transistors P11 to Pin in delay circuit 3110. Since the gate and drain of p-channel MOS transistor P31 are connected to each other, p-channel MOS transistors P31 and P11 configure a current mirror circuit. Thus, the value of the drain current flowing through each of p-channel MOS transistors P11 to P1n is the same as the value of the drain current flowing through n-channel MOS transistors N31 and N32 configuring a current mirror circuit.
Thus, the value of the current supplied to each of inverter circuits Inv.1 to Inv.n configuring delay circuit 3110 is controlled depending on the value of the current supplied to output node 3140a of variable, constant current supply circuit 3140.
An operation of synchronized signal generating circuit 3000 will now be described briefly.
For a delay time provided by delay circuit 3110 that is shorter than the time period of one cycle of external clock signal Ext.CLK, a signal output from delay circuit 3110 receiving external clock signal Ext.CLK precedes external clock signal Ext.CLK in phase. Depending on the phase difference detected in phase comparator 3120, switching decoder 3130 controls variable, constant current supply circuit 3140 by means of constant current supply switch signal CS to delay the advanced phase of the signal output from delay circuit 3110 to reduce the value of the constant current output to output node 3140a. Responsively the value of the drain current flowing through the current mirror circuit configured of n-channel MOS transistors N31 and N32 is reduced and so is the value of the current supplied to each of inverter circuits Inv.i (i=1, 2, . . . n) configuring delay circuit 3110.
Thus inverter circuits Inv.1 to Inv.n provide increased delay time and delay circuit 3110 receiving external clock signal Ext.CLK outputs a signal delayed in phase.
That is, the phase difference between external clock signal Ext.CLK and the signal output from delay circuit 3110 changes so that they are synchronized with each other.
For a delay time provided by delay circuit 3110 that is longer than the time period of one cycle of external clock signal Ext.CLK, the inverted version of the above operation can be provided to synchronize internal clock signal int.CLK output from delay circuit 3110 with external clock signal Ext.CLK.
However, the conventional, synchronized signal generation circuit 3000 configured as described above has the following disadvantages.
An DLL circuit and the like cannot be used until an external clock signal and a clock signal start to synchronize with each other, and the time required until the synchronization operation is completed is disadvantageously prolonged if the possible range of a delay control data is increased to enhance the precision of phasing.
Furthermore, in controlling the delay time of the DLL circuit or the like, a delay control data held in e.g. the decimal notation disadvantageously results in an increased number of bits and that held in the binary notation, which reduces the number of bits, disadvantageously results in an increased number of the elements of the decoder circuit and hence reduction in speed.